BibTeX
CSL-JSON
MLA
Harvard
Formal Verification of Hardware Synthesis
release_yn64trjx5zh2znhcoulsuzumzu
by
Thomas Braibant
Released
as a article
.
2013
Abstract
We report on the implementation of a certified compiler for a high-level
hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs).
Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded
atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq.
The target language of the compiler corresponds to a synthesisable subset of
Verilog or VHDL. A key aspect of our approach is that input programs to the
compiler can be defined and proved correct inside Coq. Then, we use extraction
and a Verilog back-end (written in OCaml) to get a certified version of a
hardware design.
In text/plain
format
Archived Files and Locations
application/pdf 221.0 kB
file_qguit5zzhjalfoiyugnezump7q
|
archive.org (archive) |
Read Archived PDF
Preserved and Accessible
arXiv
1301.4779v1
Work Entity
access all versions, variants, and formats of this works (eg, pre-prints)
access all versions, variants, and formats of this works (eg, pre-prints)
Cite This
Lookup Links