A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture release_ybzzxrzco5horhs5co7msf5ioa

by Niklas U. Andersson, Mark Vesterbacka

Published in IEEE Transactions on Circuits and Systems - II - Express Briefs by Institute of Electrical and Electronics Engineers (IEEE).

2014   Volume 61, Issue 10, p773-777

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