BibTeX
CSL-JSON
MLA
Harvard
Optimal Memoryless Encoding for Low Power Off-Chip Data Buses
release_wtozg2p4bfdsldivxy5kocs2lq
by
Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling
Released
as a article
.
2007
Abstract
Off-chip buses account for a significant portion of the total system power
consumed in embedded systems. Bus encoding schemes have been proposed to
minimize power dissipation, but none has been demonstrated to be optimal with
respect to any measure. In this paper, we give the first provably optimal and
explicit (polynomial-time constructible) families of memoryless codes for
minimizing bit transitions in off-chip buses. Our results imply that having
access to a clock does not make a memoryless encoding scheme that minimizes bit
transitions more powerful.
In text/plain
format
Archived Files and Locations
application/pdf 219.0 kB
file_7yqeh5dqg5govmjz7oukb3c3uu
|
archive.org (archive) |
Read Archived PDF
Preserved and Accessible
arXiv
0712.2640v1
Work Entity
access all versions, variants, and formats of this works (eg, pre-prints)
access all versions, variants, and formats of this works (eg, pre-prints)
Cite This
Lookup Links