High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND
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by
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
2021
Abstract
Ultra-reliable low-latency communication (URLLC), a major 5G New-Radio use
case, is the key enabler for applications with strict reliability and latency
requirements. These applications necessitate the use of short-length and
high-rate codes. Guessing Random Additive Noise Decoding (GRAND) is a recently
proposed Maximum Likelihood (ML) decoding technique for these short-length and
high-rate codes. Rather than decoding the received vector, GRAND tries to infer
the noise that corrupted the transmitted codeword during transmission through
the communication channel. As a result, GRAND can decode any code, structured
or unstructured. GRAND has hard-input as well as soft-input variants. Among
these variants, Ordered Reliability Bits GRAND (ORBGRAND) is a soft-input
variant that outperforms hard-input GRAND and is suitable for parallel hardware
implementation. This work reports the first hardware architecture for ORBGRAND,
which achieves an average throughput of up to 42.5 Gbps for a code length of
128 at a target FER of 10^-7. Furthermore, the proposed hardware can be
used to decode any code as long as the length and rate constraints are met. In
comparison to the GRANDAB, a hard-input variant of GRAND, the proposed
architecture enhances decoding performance by at least 2 dB. When compared to
the state-of-the-art fast dynamic successive cancellation flip decoder
(Fast-DSCF) using a 5G polar (128,105) code, the proposed ORBGRAND VLSI
implementation has 49× higher average throughput, 32× times more
energy efficiency, and 5× more area efficiency while maintaining similar
decoding performance.
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