A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions
release_pqchi5i73rff7oxm2f4mml6izq
by
Dominique Drouin, Gabriel Droulers, Marina Labalette, Bruno Lee Sang, Patrick Harvey-Collard, Abdelkader Souifi, Simon Jeannot, Stephane Monfray, Michel Pioro-Ladriere, Serge Ecoffey
Abstract
We present a versatile<jats:italic> nanodamascene</jats:italic> process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO<jats:sub>2</jats:sub>, SiO<jats:sub>2</jats:sub>, HfO<jats:sub>2</jats:sub>, Al<jats:sub>2</jats:sub>O<jats:sub>3</jats:sub>, or a combination of those. Because the<jats:italic> nanodamascene</jats:italic> technology involves processing temperatures lower than 300°C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.
In application/xml+jats
format
Archived Files and Locations
application/pdf 4.5 MB
file_aa7qigzs5zct7bkidxmvnjias4
|
web.archive.org (webarchive) savoirs.usherbrooke.ca (web) |
application/pdf 4.6 MB
file_wtxouqto4nhylnc7l2opr5dyta
|
web.archive.org (webarchive) downloads.hindawi.com (publisher) |
access all versions, variants, and formats of this works (eg, pre-prints)
Crossref Metadata (via API)
Worldcat
SHERPA/RoMEO (journal policies)
wikidata.org
CORE.ac.uk
Semantic Scholar
Google Scholar