A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions release_pqchi5i73rff7oxm2f4mml6izq

by Dominique Drouin, Gabriel Droulers, Marina Labalette, Bruno Lee Sang, Patrick Harvey-Collard, Abdelkader Souifi, Simon Jeannot, Stephane Monfray, Michel Pioro-Ladriere, Serge Ecoffey

Published in Journal of Nanomaterials by Hindawi Limited.

2017   Volume 2017, p1-8

Abstract

We present a versatile<jats:italic> nanodamascene</jats:italic> process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO<jats:sub>2</jats:sub>, SiO<jats:sub>2</jats:sub>, HfO<jats:sub>2</jats:sub>, Al<jats:sub>2</jats:sub>O<jats:sub>3</jats:sub>, or a combination of those. Because the<jats:italic> nanodamascene</jats:italic> technology involves processing temperatures lower than 300°C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.
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