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Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen release_p2dfc53e4feztnhu4r2xf64c4y

by Marcel Jacomet, Wolfgang Fichtner, Walter Guggenbühl

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title Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen
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Extra Metadata (raw JSON)

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datacite.metadataVersion 54
datacite.resourceType Dissertation
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datacite.subjects [{'subject': 'KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK)'}, {'subject': 'SIGNATURANALYSE, KOMPLEXE SCHALTUNGEN (MIKROELEKTRONIK)'}, {'subject': 'DEFEKTERKENNUNG + FEHLERERKENNUNG (ELEKTROTECHNIK)'}, {'subject': 'LAYOUTS/MIKROELEKTRONIK'}, {'subject': 'HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK)'}, {'subject': 'PRODUKTION (BETRIEBSWIRTSCHAFT)'}, {'subject': 'QUALITÄTSKONTROLLE + FERTIGUNGSPRÜFUNG'}, {'subject': 'COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS)'}, {'subject': 'SIGNATURE ANALYSIS, COMPLEX CIRCUITS (MICROELECTRONICS)'}, {'subject': 'DEFECT RECOGNITION + FAULT RECOGNITION (ELECTRICAL ENGINEERING)'}, {'subject': 'LAYOUTS/MICROELECTRONICS'}, {'subject': 'VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS)'}, {'subject': 'PRODUCTION (BUSINESS ECONOMICS)'}, {'subject': 'QUALITY CONTROL + PRODUCTION INSPECTION'}, {'subject': 'info:eu-repo/classification/ddc/621.3'}, {'subject': 'Electric engineering'}]