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A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 $\mu{\rm m}$ CMOS
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by
Mahdi Shabany, Dimpesh Patel, P. Glenn Gulak
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in IEEE Transactions on Circuits and Systems Part 1: Regular Papers by Institute of Electrical and Electronics Engineers (IEEE).
2013 Volume 60, p327-340
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