A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 $\mu{\rm m}$ CMOS release_ot543xnij5cu7pg3zlqgu4vllm

by Mahdi Shabany, Dimpesh Patel, P. Glenn Gulak

Published in IEEE Transactions on Circuits and Systems Part 1: Regular Papers by Institute of Electrical and Electronics Engineers (IEEE).

2013   Volume 60, p327-340

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