A design flow for configurable embedded processors based on optimized instruction set extension synthesis release_oqrqnrl7n5dfzdfmn2ulosmaxa

by R. Leupers, K. Karuri, S. Kraemer, M. Pandey

Published in Design, Automation, and Test in Europe by IEEE.

2006   p581-586

Archived Files and Locations

application/pdf  252.4 kB
file_u5etpxxx4bhutdsix4qpqtxc6u
web.archive.org (webarchive)
www.ice.rwth-aachen.de (web)
Read Archived PDF
Preserved and Accessible
Type  paper-conference
Stage   published
Year   2006
Work Entity
access all versions, variants, and formats of this works (eg, pre-prints)
Catalog Record
Revision: 3da8f588-4b9e-4388-a288-498c63bc12e2
API URL: JSON