Designing and Simulation of High Speed Area Efficient Full Adder Using Transmission Gates Logic release_erbipoggrjgsdjxmgwn3t3q3tu

by Swadesh Dubey, Dilip Ahirwar, Susmita Bilani, R Pandey, M-Tech Scholar

References

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Showing 1 - 13 of 13 references (in 34ms)
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Analysis of various approaches used for the implementation of QCA based full adder circuit
Manisha G. Waje, P.K. Dakhole
2016   2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)  unpublished
doi:10.1109/iceeot.2016.7755129 
[b1]

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Reliability-aware design for programmable QCA logic with scalable clocking circuit
Bibhash Sen, Mayukh R. Chowdhury, Rijoy Mukherjee, Mrinal Goswami, Biplab K. Sikdar
2017   Journal of Computational Electronics
doi:10.1007/s10825-017-0973-z 
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Two new energy-efficient full adder designs
Majid Amini Valashani, Sattar Mirzakuchaki
2016   2016 24th Iranian Conference on Electrical Engineering (ICEE)  unpublished
doi:10.1109/iraniancee.2016.7585603 
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Iranian Conference on Electrical Engineering
2016  
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Energy efficient low power high speed full adder design using hybrid logic
M Nikhil Theja, T Balakumaran
2016   2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)  unpublished
doi:10.1109/iccpct.2016.7530209 
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Low power array multiplier using modified full adder
S. Srikanth, I. Thahira Banu, G. Vishnu Priya, G. Usha
2016   2016 IEEE International Conference on Engineering and Technology (ICETECH)  unpublished
doi:10.1109/icetech.2016.7569408 
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Verilog design of full adder based on reversible gates
Varun Pratap Singh, Manish Rai
2016   2016 2nd International Conference on Advances in Computing, Communication, & Automation (ICACCA) (Fall)  unpublished
doi:10.1109/icaccaf.2016.7748977 
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Comparison Analysis of FINFET Based 1-Bit Full Adder Cell Implemented Using Different Logic Styles at 10, 22 and 32nm
Shivani Sharma , Gaurav Soni
2016  
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Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
Ramin Rajaei, Sina Bakhtavari Mamaghani
2017   IEEE transactions on device and materials reliability
doi:10.1109/tdmr.2016.2644721 
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Design of high speed and low power full adder in sub-threshold region
Sambhu Nath Pradhan, Vivek Rai, Angshuman Chakraborty
2016   2016 International Conference on Microelectronics, Computing and Communications (MicroCom)  unpublished
doi:10.1109/microcom.2016.7522411 
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Design of low power high speed full adder cell with XOR/XNOR logic gates
Sudhakar Alluri, M. Dasharatha, B. Rajendra Naik, N. S. S. Reddy
2016   2016 International Conference on Communication and Signal Processing (ICCSP)  unpublished
doi:10.1109/iccsp.2016.7754203 
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Energy Efficient Full Adder Using Modified GDI and MVT Scheme in 45nm Technology
Krishnendu Dhar
2014  
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A new design of low power high speed hybrid CMOS full adder
Mayur Agarwal, Neha Agrawal, Md. Anis Alam
2014   2014 International Conference on Signal Processing and Integrated Networks (SPIN)  unpublished
doi:10.1109/spin.2014.6776995