Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique release_6fsqvkaq4nbbjkvd3h3cxuqlqy

by S. K. Manikandan, C. Palanisamy

Published in Circuits and Systems by Scientific Research Publishing, Inc,.

2016   Volume 07, Issue 09, p2593-2602

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