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IEEE/ACM International Symposium on Nanoscale Architectures
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Homepage URLs
http://nanoarch.org/ |
Example Publications
A new Tunnel-FET based RAM concept for ultra-low power applications
Mostafizur Rahman, Mingyu Li, Jiajun Shi, Santosh Khasanvis, C. Andras Moritz
2014
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IEEE/ACM International Symposium on Nanoscale Architectures
doi:10.1109/nanoarch.2014.6880505 dblp:conf/nanoarch/RahmanLSKM14
Analysis of STT-RAM cell design with multiple MTJs per access
Henry Park, Richard Dorrance, Amr Amin, Fengbo Ren, Dejan Markovic, C.K. Ken Yang
2011
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IEEE/ACM International Symposium on Nanoscale Architectures
doi:10.1109/nanoarch.2011.5941483 dblp:conf/nanoarch/ParkDHRMY11
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design
Pilin Junsangsri, Fabrizio Lombardi, Jie Han
2014
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IEEE/ACM International Symposium on Nanoscale Architectures
doi:10.1109/nanoarch.2014.6880477 dblp:conf/nanoarch/JunsangsriLH14a
Hierarchical composition of memristive networks for real-time computing
Jens Burger, Alireza Goudarzi, Darko Stefanovic, Christof Teuscher
2015
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IEEE/ACM International Symposium on Nanoscale Architectures
doi:10.1109/nanoarch.2015.7180583 dblp:conf/nanoarch/BurgerGST15
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni
2011
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IEEE/ACM International Symposium on Nanoscale Architectures
doi:10.1109/nanoarch.2011.5941482 dblp:conf/nanoarch/SaripalliDNK11